3.4.1 A Schottky diode with an interfacial layer

Table of Contents - 1 2 3 4 5 6 7 8 9 R S ¬ ­ ®
In this Section

  1. Introduction
  2. Capacitance analysis
  3. Current analysis
  4. Summary

3.4.1.1 Introduction

An interfacial layer between the metal and semiconductor of a Schottky diode affects the measured barrier height and built-in potential. The total potential within the device is now divided between the interfacial layer and the semiconductor. This causes the potential across the semiconductor to be lower so that carriers can more easily flow from the semiconductor into the metal, yielding a larger current. The interfacial layer also reduces the capacitance.

As an example we consider a thin 3 nm thick oxide layer in a gold-silicon Schottky diode. The energy band diagram is shown in the figure below.

3.4.1.2 Capacitance analysis

Since the interfacial layer can be viewed as an additional capacitor connected in series with the capacitance associated with the depletion layer capacitance, it is easy to accept that the total capacitance is lower than for a diode without interfacial layer. A 1/C2 plot versus the applied voltage is shown in the figure below.

This plot reveals that the slope remains the same, while the intercept with the voltage axis shifts to higher forward voltages. The fact that the slope remains unchanged is due to the fact that it depends on the doping concentration in the semiconductor, which remains unchanged. The presence of an interfacial layer therefore increases the measured built-in potential, but does not alter the extracted doping concentration.

3.4.1.3 Current analysis

The analysis of the forward bias current is more complex since it the depends on the transport properties of the interfacial layer. However if one assumes that the barrier is so thin that carriers can easily tunnel through, the diode current analysis can be obtained from the standard diffusion analysis, provided that the altered potential across the semiconductor is taken into account.

A comparsion of a gold-silicon diode with and without an interfacial layer is shown in the figure below. The figure reveals that the interfacial layer affects both the slope and the intercept of the forward-biased current-voltage when plotted on a semi-logarithmic scale.

3.4.1.4 Summary

In summary, an interfacial layer increases the built-in potential as measured with a C-V measurement, decreases the internal potential across the semiconductor which increases the measured ideality factor and saturation current. It also decreases the measured barrier height as extracted from the temperature dependence of the saturation current and limits the maximum current density.
3.4 ¬ ­ ® 3.4.2
© Bart Van Zeghbroeck, 1998